By Henning Stichtenoth (auth.), M. Anwar Hasan, Tor Helleseth (eds.)

This publication constitutes the refereed lawsuits of the 3rd overseas Workshop at the mathematics of Finite Fields, WAIFI 2010, held in Istanbul, Turkey, in June 2010. The 15 revised complete papers provided have been rigorously reviewed and chosen from 33 submissions. The papers are equipped in topical sections on effective finite box mathematics, pseudo-random numbers and sequences, Boolean features, services, Equations and modular multiplication, finite box mathematics for pairing dependent cryptography, and finite box, cryptography and coding.

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Extra resources for Arithmetic of Finite Fields: Third International Workshop, WAIFI 2010, Istanbul, Turkey, June 27-30, 2010. Proceedings

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We considered Montgomery multiplication and various special reduction routines which are of interest for elliptic curve cryptography. 5 times faster compared to general purpose Montgomery multiplication for the same bitsize. The performance results of our multi-stream modular multiplication implementations for the synergistic processing elements of the Cell broadband engine architecture set new performance records for moduli of bit-length in the range [192, 521] on this platform. g. in batch elliptic curve decryption.

A radix-213 system is used to represent 195-bit integers using 15 limbs, this has the advantage of accumulating multiple carries before an overflow occurs (on the SPE architecture) compared to a radix-216 system but requires more limbs to represent the integers. When quadratically scaling our 192-bit performance result, in a similar fashion as done in [3], this 2 leads to an estimate of 176 · ( 195 192 ) = 182 cycles; this is slightly faster compared to the 189 required cycles reported in [3]. Discussion.

2 and 3 are written in VHDL. We have implemented the original (DLGMp) and the modified digit-level multipliers (MDLGMp) on the Xilinx® Virtex5™ FPGA family with target device xc5vlx330-2ff1760 for GF (2163 ) and GF (2283 ) fields. Correctness of the implementations is verified by performing functional simulations using the Quartus® II software. We have synthesized both multipliers for several different digit sizes A Modified Low Complexity Digit-Level Gaussian Normal Basis Multiplier 37 Table 3. FPGA implementation results for propagation delay (in terms of nano second) and area (in terms of number of slices) for different digit sizes with m = 163 and T = 4.

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